{"id":19,"date":"2024-05-02T09:21:31","date_gmt":"2024-05-02T09:21:31","guid":{"rendered":"http:\/\/140.112.17.235\/wordpress\/?page_id=19"},"modified":"2024-08-17T02:22:23","modified_gmt":"2024-08-17T02:22:23","slug":"journal-articles","status":"publish","type":"page","link":"http:\/\/140.112.17.235\/wordpress\/index.php\/journal-articles\/","title":{"rendered":"Journal Articles"},"content":{"rendered":"\n<ul>\n<li>G. -Y. Chen and T. -C. Lee, &#8220;<strong>An 8 Gb\/s Far-End Crosstalk Cancelation and FFE Co-Designed TX Output Driver<\/strong>,&#8221; in IEEE Solid-State Circuits Letters, vol. 7, pp. 227-230, 2024<\/li>\n\n\n\n<li>Y. -H. Yang and T. -C. Lee, &#8220;<strong>A Sub-Baud-Rate Wireline Receiver With One-Tap DFE<\/strong>,&#8221; in\u00a0<em>IEEE Journal of Solid-State Circuits<\/em>,2024 <strong>(Early Access)<\/strong><\/li>\n\n\n\n<li>H. -H. Chang, C. -R. Chen and T. -C. Lee, &#8220;<strong>A 511-&nbsp;\u03bc&nbsp;W 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique<\/strong>,&#8221; in&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>,2024 <strong>(Early Access)<\/strong><\/li>\n\n\n\n<li>Y. -C. Chan, C. -W. Chang and T. -C. Lee, &#8220;<strong>A 0.9-V 50-MS\/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator<\/strong>,&#8221; in&nbsp;<em>IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 70, no. 9, pp. 3263-3267, Sept. 2023<\/li>\n\n\n\n<li>Y. -H. Yang, M. Tzou and T. -C. Lee, &#8220;<strong>A 6.0\u201311.0 Gb\/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique<\/strong>,&#8221; in&nbsp;<em>IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 70, no. 2, pp. 386-390, Feb. 2023<\/li>\n\n\n\n<li>H. -H. Chang, T. -C. Lin and T. -C. Lee, &#8220;<strong>A Single-Channel 1-GS\/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier<\/strong>,&#8221; in&nbsp;<em>IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 69, no. 4, pp. 2021-2025, April 2022<\/li>\n\n\n\n<li>Y. -H. Yang and T. -C. Lee, &#8220;<strong>A Wireline Termination Embedded Energy Harvesting System With 300-\u03bcW Extracted<\/strong>,&#8221; in&nbsp;<em>IEEE Solid-State Circuits Letters<\/em>, vol. 3, pp. 438-441, 2020 (Invited)<\/li>\n\n\n\n<li>C. -Y. Lin, Y. -H. Wei and T. -C. Lee, &#8220;<strong>A 10-bit 2.6-GS\/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique<\/strong>,&#8221; in&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, vol. 53, no. 5, pp. 1508-1517, May 2018<\/li>\n\n\n\n<li>C. -T. Tsai&nbsp;<em>et al<\/em>., &#8220;<strong>Multi-Mode VCSEL Chip with High-Indium-Density InGaAs\/AlGaAs Quantum-Well Pairs for QAM-OFDM in Multi-Mode Fiber<\/strong>,&#8221; in&nbsp;<em>IEEE Journal of Quantum Electronics<\/em>, vol. 53, no. 4, pp. 1-8, Aug. 2017, Art no. 2400608<\/li>\n\n\n\n<li>W. -S. Chang and T. -C. Lee, &#8220;<strong>A 5 GHz Fractional-<\/strong><strong>N<\/strong><strong>&nbsp;ADC-Based Digital Phase-Locked Loops With \u2212243.8 dB FOM<\/strong>,&#8221; in&nbsp;<em>IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 63, no. 11, pp. 1845-1853, Nov. 2016<\/li>\n\n\n\n<li>C. -Y. Lin and T. -C. Lee, &#8220;<strong>A 12-bit 210-MS\/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique<\/strong>,&#8221; in&nbsp;<em>IEEE Transactions on Circuits and Systems I: Regular Papers<\/em>, vol. 63, no. 7, pp. 929-938, July 2016<\/li>\n\n\n\n<li>C. -Y. Lin, C. -H. Wong, C. -H. Hsu, Y. -H. Wei and T. -C. Lee, &#8220;<strong>A 200-MS\/s Phase-Detector-Based Comparator With 400-<\/strong><strong>\u03bc<\/strong><strong>V<\/strong><strong>rms<\/strong><strong>&nbsp;Noise<\/strong>,&#8221; in&nbsp;<em>IEEE Transactions on Circuits and Systems II: Express Briefs<\/em>, vol. 63, no. 9, pp. 813-817, Sept. 2016<\/li>\n\n\n\n<li>W-S Chang, P-C Hung and T-C Lee, \u201c<strong>A Fractional-N Diver-Less Phase-Locked Loop With a Subsampling Phase Detector<\/strong>\u201d <em>IEEE Journal of Solid-State Circuits<\/em>, Nov. 2014<\/li>\n\n\n\n<li>C-C Lee and T-C Lee, \u201c<strong>A 2.4-GHz High Efficiency Adaptive Power Harvester<\/strong>,\u201d<em>IEEE Transactions on Very Large Scale Integration Systems<\/em>, Feb. 2014<\/li>\n\n\n\n<li>C-H Wong and T-C Lee, \u201c<strong>A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator<\/strong>,\u201d<em>IEEE Transactions on Circuits and Systems, Part I<\/em>, vol. 58, no. 3, pp. 1264-1273, May 2013<\/li>\n\n\n\n<li>C-D Su, C-W Lee and T-C Lee, \u201c<strong>A 6-GHz All Digital PLL for Spread Spectrum Clock Generators(SSCG)<\/strong>,\u201d&nbsp;<em>International Journal of Electrical Engineering<\/em>, Jun. 2012<\/li>\n\n\n\n<li>Y-C Huang and T-C Lee, \u201c<strong>A 10-bit 100 MS\/s 4.5 mW Pipelined ADC with a Time Sharing Techniques<\/strong>,\u201d&nbsp;<em>IEEE Transactions on Circuits and Systems, Part I<\/em>, pp. 1157-1166, Jun. 2011<\/li>\n\n\n\n<li>Z-Z Chen and T-C Lee, \u201c<strong>The Design and Analysis of Dual-Delay-Path Ring Oscillators<\/strong>,\u201d&nbsp;<em>IEEE Transactions on Circuits and Systems, Part I<\/em>, Mar. 2011<\/li>\n\n\n\n<li>Z-Z Chen and T-C Lee, \u201c<strong>The Study of a Dual-Mode Ring Oscillator<\/strong>,\u201d&nbsp;<em>IEEE Transactions on Circuits and Systems, Part II<\/em>, 2011<\/li>\n\n\n\n<li>T-C Lee and C-H Lin, \u201c<strong>Nonlinear R-2R Transistor-Only DAC<\/strong>,\u201d&nbsp;<em>IEEE Transactions on Circuits and Systems, Part I<\/em>, Nov. 2010<\/li>\n\n\n\n<li>K-T Chen and T-C Lee, \u201c<strong>A 320-MHz CMOS Continuous-Time \u0394\u03a3 Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB<\/strong>,\u201d<em> International Journal of Electrical Engineering<\/em>, Jun. 2010<\/li>\n\n\n\n<li>Yen-Chuan Huang and Tai-Cheng Lee, \u201c<strong>A 0.02-mm2 9-bit 50-MS\/s Cyclic ADC in a 90-nm Digital CMOS Technology<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Mar. 2010<\/li>\n\n\n\n<li>Li-Han Hung; Tai-Cheng Lee, \u201c<strong>A Split-Based Digital Background Calibration Technique in Pipelined ADCs<\/strong>,\u201d&nbsp;<em>IEEE Transactions on Circuits and Systems, Part II<\/em>, Nov. 2009<\/li>\n\n\n\n<li>K-J Hsian and Tai-Cheng Lee, \u201c<strong>A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Sept. 2009<\/li>\n\n\n\n<li>Zuow-Zun Chen and Tai-Cheng Lee, \u201c<strong>A Multiphase Compensation Method with Dynamic Element Matching Technique in S-D Fractional-N Frequency Synthesizers<\/strong>,\u201d&nbsp;<em>Journal of Semiconductor Technology and Science<\/em>, Sept. 2008<\/li>\n\n\n\n<li>K-J Hsiao and T-C Lee, \u201c<strong>A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Jun. 2008<\/li>\n\n\n\n<li>D.-L. Shen and T.-C. Lee, \u201c<strong>A 6-b 800-MS\/s Pipelined A\/D Converter with Open-Loop Amplifiers<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Feb. 2007<\/li>\n\n\n\n<li>T.-C. Lee and Y.-C. Huang, \u201c<strong>The design and analysis of a Miller Divider Based Clock Generator for MBOA-UWB Application<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Jun. 2006<\/li>\n\n\n\n<li>T.-C. Lee and K.-J. Hsiao, \u201c<strong>The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Jun. 2006<\/li>\n\n\n\n<li>T.-C. Lee and C.-C. Chen, \u201c<strong>A Mixed-Signal GFSK Demodulator for Bluetooth<\/strong>,\u201d&nbsp;<em>IEEE Transactions on Circuits and Systems Part II<\/em>, Mar. 2006<\/li>\n\n\n\n<li>T. C. Lee and B. Razavi, \u201c<strong>A Stabilization Technique for Phase-Locked Frequency Synthesizers<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Jun. 2003<\/li>\n\n\n\n<li>T. C. Lee and B. Razavi, \u201c<strong>A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire<\/strong>,\u201d&nbsp;<em>IEEE Journal of Solid-State Circuits<\/em>, Mar. 2001<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"_links":{"self":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages\/19"}],"collection":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/comments?post=19"}],"version-history":[{"count":6,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages\/19\/revisions"}],"predecessor-version":[{"id":125,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages\/19\/revisions\/125"}],"wp:attachment":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/media?parent=19"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}