{"id":17,"date":"2024-05-02T09:21:11","date_gmt":"2024-05-02T09:21:11","guid":{"rendered":"http:\/\/140.112.17.235\/wordpress\/?page_id=17"},"modified":"2024-05-03T06:47:20","modified_gmt":"2024-05-03T06:47:20","slug":"conference-papers","status":"publish","type":"page","link":"http:\/\/140.112.17.235\/wordpress\/index.php\/conference-papers\/","title":{"rendered":"Conference Papers"},"content":{"rendered":"\n<ul>\n<li>C. -T. Chen, Y. -H. Yang and T. -C. Lee, &#8220;<strong>A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth<\/strong>,&#8221;&nbsp;<em>2022 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, Austin, TX, USA, 2022<\/li>\n\n\n\n<li>Y. -P. Lai, H. -H. Chang and T. -C. Lee, &#8220;<strong>An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter<\/strong>,&#8221;&nbsp;<em>2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)<\/em>, Hsinchu, Taiwan, 2022<\/li>\n\n\n\n<li>K. -R. Li, W. -S. Chang and T. -C. Lee, &#8220;<strong>A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique<\/strong>,&#8221;&nbsp;<em>2020 IEEE International Symposium on Circuits and Systems (ISCAS)<\/em>, Seville, Spain, 2020<\/li>\n\n\n\n<li>H. -C. Cheng, Y. -H. Yang and T. -C. Lee, &#8220;<strong>Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop<\/strong>,&#8221;\u00a0<em>2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)<\/em>, Hsinchu, Taiwan, 2020<\/li>\n\n\n\n<li>Y. -H. Yang and T. -C. Lee, &#8220;<strong>A Wireline Termination Embedded Energy Harvesting System With 300-\u03bcW Extracted<\/strong>,&#8221;<em>2020 IEEE Asian Solid-State Circuits Conference (A-SSCC)<\/em>, Hiroshima, Japan, 2020<\/li>\n\n\n\n<li>H. -H. Ting and T. -C. Lee, &#8220;<strong>25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique<\/strong>,&#8221;&nbsp;<em>2020 IEEE International Solid-State Circuits Conference &#8211; (ISSCC)<\/em>, San Francisco, CA, USA, 2020<\/li>\n\n\n\n<li>Y. -L. Hsieh and T. -C. Lee, &#8220;<strong>A SAR-Assisted Continuous-Time Incremental \u03a3\u0394 ADC With First-Order Noise Coupling<\/strong>,&#8221;&nbsp;<em>2019 IEEE 13th International Conference on ASIC (ASICON)<\/em>, Chongqing, China, 2019<\/li>\n\n\n\n<li>W. -S. Chang, D. -E. Jhou, Y. -H. Yang and T. -C. Lee, &#8220;<strong>An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique<\/strong>,&#8221;&nbsp;<em>2017 IEEE Asian Solid-State Circuits Conference (A-SSCC)<\/em>, Seoul, Korea (South), 2017<\/li>\n\n\n\n<li>J. -C. Hsiao, D. -E. Jhou and T. -C. Lee, &#8220;<strong>A 10-Gb\/s equalizer with digital adaptation<\/strong>,&#8221;&nbsp;<em>2017 International SoC Design Conference (ISOCC)<\/em>, Seoul, Korea (South), 2017<\/li>\n\n\n\n<li>D. -E. Jhou, W. -S. Chang and T. -C. Lee, &#8220;<strong>A 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based MDLL<\/strong>,&#8221;&nbsp;<em>2017 Symposium on VLSI Circuits<\/em>, Kyoto, Japan, 2017<\/li>\n\n\n\n<li>H. -Y. Kao&nbsp;<em>et al<\/em>., &#8220;<strong>Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit\/s for 100-m OM4 MMF link<\/strong>,&#8221;&nbsp;<em>2017 Optical Fiber Communications Conference and Exhibition (OFC)<\/em>, Los Angeles, CA, USA, 2017<\/li>\n\n\n\n<li>C. -L. Chang and T. -C. Lee, &#8220;<strong>An thermoelectric and RF multi-source energy harvesting system<\/strong>,&#8221;&nbsp;<em>2016 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG)<\/em>, Prague, Czech Republic, 2016<\/li>\n\n\n\n<li>Y. -H. Wei, C. -Y. Lin and T. -C. Lee, &#8220;<strong>A 12-bit 600-MS\/s time-interleaved SAR ADC with background timing skew calibration<\/strong>,&#8221;&nbsp;<em>2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)<\/em>, Taipei, Taiwan, 2016<\/li>\n\n\n\n<li>C. -P. Wang and T. -C. Lee, &#8220;<strong>A technique for in-band phase noise reduction in fractional-N frequency synthesizers<\/strong>,&#8221;&nbsp;<em>2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)<\/em>, Toyama, Japan, 2016<\/li>\n\n\n\n<li>B-J Lin, W-S Chang and T-C Lee, \u201c<strong>A 2x25Gb\/s 20mW Serializing Transmitter with 2.5:1 Multiplexers in 40nm Technology<\/strong>\u201d<em>IEEE International Symposium on VLSI Design, Automation and Test<\/em>, April 2016<\/li>\n\n\n\n<li>C-Y Lin, Y-H Wei and T-C Lee, \u201c<strong>A 10b 2.6GS\/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration<\/strong>\u201d<em> International Solid-State Circuit Conference<\/em>, San Francisco, Feb. 2016<\/li>\n\n\n\n<li>C-K Hsu and T-C Lee, \u201c <strong>A Single-Channel 10-b 400-MS\/s 8.7-mW Pipeline ADC in a 90-nm Technology<\/strong>\u201d <em>IEEE Asian Solid-State Circuit Conference<\/em>, Nov. 2015<\/li>\n\n\n\n<li>T-Y Wang and T-C Lee, \u201c<strong>A 84.7-DR wide BW incremental ADC using&nbsp; CT structure<\/strong>\u201d<em> IEEE International Symposium on VLSI Design, Automation and Test<\/em>, April 2015<\/li>\n\n\n\n<li>C-L Chang and T-C Lee, \u201c<strong>A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability<\/strong>\u201d <em>IEEE International Symposium on Integrated Circuits<\/em>, Dec. 2014<\/li>\n\n\n\n<li>L-H Chiueh and T-C Lee, \u201c<strong>A 6-Gb\/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit<\/strong>\u201d <em>IEEE Asian Solid-State Circuit Conference<\/em>, Nov. 2014<\/li>\n\n\n\n<li>C-Y Lin and T-C Lee, \u201c<strong>A 12-bit 210-MS\/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique<\/strong>\u201d <em>IEEE Symposium on VLSI Circuits Digest of Technical Papers<\/em>, June 2014<\/li>\n\n\n\n<li>J-A Jheng, W-S Chang and T-C Lee, \u201c<strong>A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth<\/strong><em>\u201d IEEE International Symposium on VLSI Design, Automation and Test<\/em>, April 2014.<\/li>\n\n\n\n<li>P-C Huang, W-S Chang and T-C Lee, \u201c<strong>A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc\/Hz In-Band Phase Noise<\/strong>,\u201d&nbsp;<em>International Solid-State Circuit Conference<\/em>, San Francisco, Feb. 2014<\/li>\n\n\n\n<li>C-Y Lin and T-C Lee, \u201c<strong>Jitter Error Cancellation Technique in Digital Domain for ADC<\/strong>,\u201d&nbsp;<em>IEEE VLSI-DAT<\/em>, Apr. 2013<\/li>\n\n\n\n<li>C-Y Lin Y-C Huang and T-C Lee, \u201c<strong>Analysis of the Leakage Effect in a Pipelined ADC with Nanoscale CMOS Technologies<\/strong>,\u201d&nbsp;<em>IEEE VLSI-DAT<\/em>, Apr. 2013<\/li>\n\n\n\n<li>C-C Ho and T-C Lee, \u201c<strong>A 10-bit 200-MS\/s Reconfigurable Pipelined A\/D Converter<\/strong>,\u201d&nbsp;<em>IEEE VLSI DAT<\/em>, Apr. 2012<\/li>\n\n\n\n<li>Y-C Huang, C-Y Lin and T-C Lee, \u201c<strong>A 10-b 400Ms\/s 36mW interleaved ADC<\/strong>,\u201d&nbsp;<em>IEEE RFIT Symposium<\/em>, Dec. 2011<\/li>\n\n\n\n<li>P Zhang, T-C Lee, \u201c<strong>Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS<\/strong>,\u201d&nbsp;<em>International Conference on Sampling Theory and Applications<\/em>, May 2011<\/li>\n\n\n\n<li>K Fong, Z-Z Chen and T-C Le, \u201c<strong>An All<\/strong><strong>\u2010<\/strong><strong>Digital De\u2010skew Clock Generator for Arbitrary Wide Range Delay<\/strong>,\u201d&nbsp;<em>IEEE Asian Pacific Conference on Circuits and Systems<\/em>, Dec. 2010<\/li>\n\n\n\n<li>Y-C Hung, K Fong and T-C Lee, \u201c<strong>A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay<\/strong>,\u201d&nbsp;<em>IEEE Asian Solid-State Circuit Conference<\/em>, Nov. 2010<\/li>\n\n\n\n<li>C-Y Lin, C-Y Chiang and T-C Lee, \u201c<strong>An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III<\/strong>,\u201d&nbsp;<em>IEEE Custom Integrated Circuits Conference<\/em>, Sept. 2010<\/li>\n\n\n\n<li>Yen-Chuang Huang and Tai-Cheng Lee, \u201c<strong>A 10-bit 100 MS\/s 4.5 mW Pipelined ADC with a Time Sharing Techniques<\/strong>,\u201d&nbsp;<em>International Solid-State Circuit Conference<\/em>, San Francisco, Feb. 2010<\/li>\n\n\n\n<li>Feng-Chiu Hsieh and Tai-Cheng, \u201c<strong>A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification<\/strong>,\u201d&nbsp;<em>IEEE Asian Solid-State Circuit Conference<\/em>, Fukuoka, Japan, Nov. 2008<\/li>\n\n\n\n<li>Shih-Chun Lin and Tai-Cheng Lee, \u201c<strong>An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits<\/strong>,\u201d&nbsp;<em>IEEE Aisan Solid-State Circuit Conference<\/em>, Fukuoka, Japan, Nov. 2008<\/li>\n\n\n\n<li>K-J Hsiao, M-H Lee and T-C Lee, \u201c<strong>A CLOCK AND DATA RECOVERY CIRCUIT WITHWIDE LINEAR RANGE FREQUENCY<\/strong>,\u201d&nbsp;<em>IEEE VLSI-DAT<\/em>, Apr. 2008<\/li>\n\n\n\n<li>Y-C Huang, Q-T Chen and T-C Lee, \u201c<strong>A 4-PAM Adaptive Analog Equalizer for Backplane Interconnections<\/strong>,\u201d&nbsp;<em>IEEE VLSI-DAT<\/em>, Apr. 2008<\/li>\n\n\n\n<li>K-J Hsiao and T.-C. Lee, \u201c<strong>A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation<\/strong>,\u201d&nbsp;<em>IEEE International Solid-State Circuit Conference<\/em>, Feb. 2008<\/li>\n\n\n\n<li>D.-L Shen, Y-C Lai and T.-C. Lee, \u201c<strong>A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration<\/strong>,\u201d&nbsp;<em>IEEE Asian Solid-State Circuit Conference<\/em>, Nov. 2007<\/li>\n\n\n\n<li>K-J Hsiao and T-C Lee, \u201c<strong>A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning<\/strong>,\u201d&nbsp;<em>Symposium on VLSI Circuits<\/em>, Jun. 2007<\/li>\n\n\n\n<li>G-J Chen, H-H Chiu and T-C Lee, \u201c<strong>A 4-Channel Poly-Phase Filter for Cognitive Radio Systems<\/strong>,\u201d&nbsp;<em>IEEE VLSI-DAT<\/em>, Apr. 2007<\/li>\n\n\n\n<li>H-S Kao, M-J Yang, T-C Lee, \u201c<strong>A Delay-Line-Based GFSK Demodulator for Low-IF Receivers<\/strong>,\u201d&nbsp;<em>International Solid-State Circuit Conference (ISSCC)<\/em>, Feb. 2007<\/li>\n\n\n\n<li>Q.-T. Chen, Y.-C. Huang and T.-C. Lee, \u201c<strong>A 14Gb\/s 4PAM Adaptive Analog Equalizer for 40-inch Backplane Interconnections<\/strong>,\u201d&nbsp;<em>Asian Solid-State Circuit Conference (ASSCC)<\/em>, Nov. 2006<\/li>\n\n\n\n<li>D-L Shen and T-C Lee, \u201c<strong>A 6-b 800-MS\/s Pipelined A\/D Converter with Open-loop Amplifiers<\/strong>,\u201d&nbsp;<em>IEEE Symposium on VLSI Circuits<\/em>, Jun. 2006<\/li>\n\n\n\n<li>Y-M Liao and T-C Lee, \u201c<strong>A 6-b 1.3Gs\/s A\/D Converter with C-2C Switch\u2013Capacitor Technique<\/strong>,\u201d&nbsp;<em>IEEE VLSI-DAT<\/em>, Apr. 2006<\/li>\n\n\n\n<li>T.-C. Lee and W.-L. Lee, \u201c<strong>A Spur-Suppression Technique for Phase-Locked Frequency Synthesizers<\/strong>,\u201d&nbsp;<em>IEEE International Solid-State Circuit Conference (ISSCC)<\/em>, Feb. 2006<\/li>\n\n\n\n<li>T.-C. Lee and etal, \u201c<strong>A 40-GHz Distributed-Load Static Divider<\/strong>,\u201d&nbsp;<em>IEEE Asian Solid-State Circuit Conference<\/em>, Nov. 2005<\/li>\n\n\n\n<li>T. C. Lee and K-J Hsiao, \u201c<strong>A DLL-Based Frequency Multiplier For MBOA-UWB System<\/strong>,\u201d&nbsp;<em>IEEE Symposium on VLSI Circuits<\/em>, Jun. 2005<\/li>\n\n\n\n<li>T. C. Lee and Y. C. Huang, \u201c<strong>A Miller Divider Based Clock Generator for MBOA-UWB Application<\/strong>,\u201d&nbsp;<em>IEEE Symposium on VLSI Circuits<\/em>, Jun. 2005<\/li>\n\n\n\n<li>D. L. Shen and T. C. Lee, \u201c<strong>A Linear-Approximation Technique for Digitally-Calibrated Pipelined ADCs<\/strong>,\u201d&nbsp;<em>ISCAS<\/em>, May 2005<\/li>\n\n\n\n<li>T. C. Lee and Y. C. Huang, \u201c<strong>An Optimization Technique for RF Buffers with Active Inductors<\/strong>,\u201d&nbsp;<em>ISCAS<\/em>, May 2005<\/li>\n\n\n\n<li>Y. H. Chen, and T. C. Lee, \u201c<strong>6 bits 500-Ms\/s Digital Self-Calibrated Pipelined Analog-to-Digital Converter<\/strong>,\u201d&nbsp;<em>AP-ASIC<\/em>, pp98-101, Aug. 2004<\/li>\n\n\n\n<li>H. C. Wang, H. S. Kao, and T. C. Lee, \u201c<strong>An 8-bit 2-V 2-mW 0.25-mm2 CMOS DAC<\/strong>,\u201d&nbsp;<em>AP-ASIC<\/em>, pp. 102-105, Aug. 2004<\/li>\n\n\n\n<li>T. C. Lee and B. Razavi, \u201c<strong>A Stabilization Technique for Phase-Locked Frequency Synthesizers<\/strong>,\u201d&nbsp;<em>IEEE VLSI Circuits Symposium<\/em>, Kyoto, Japan, Jun. 2001<\/li>\n\n\n\n<li>T. C. Lee and B. Razavi, \u201c<strong>A 125-MHz Mixed-Signal Equalizer for Gigabit Ethernet on Copper Wire<\/strong>,\u201d&nbsp;<em>IEEE Custom Integrated Circuits Conference<\/em>, San Diego, May 2001<\/li>\n\n\n\n<li>T. C. Lee and B. Razavi, \u201c<strong>A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire<\/strong>,\u201d&nbsp;<em>IEEE Custom Integrated Circuits Conference<\/em>, Orlando, May 2000<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"_links":{"self":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages\/17"}],"collection":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/comments?post=17"}],"version-history":[{"count":3,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages\/17\/revisions"}],"predecessor-version":[{"id":105,"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/pages\/17\/revisions\/105"}],"wp:attachment":[{"href":"http:\/\/140.112.17.235\/wordpress\/index.php\/wp-json\/wp\/v2\/media?parent=17"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}