Journal Articles

  • G. -Y. Chen and T. -C. Lee, “An 8 Gb/s Far-End Crosstalk Cancelation and FFE Co-Designed TX Output Driver,” in IEEE Solid-State Circuits Letters, vol. 7, pp. 227-230, 2024
  • Y. -H. Yang and T. -C. Lee, “A Sub-Baud-Rate Wireline Receiver With One-Tap DFE,” in IEEE Journal of Solid-State Circuits,2024 (Early Access)
  • H. -H. Chang, C. -R. Chen and T. -C. Lee, “A 511- μ W 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique,” in IEEE Journal of Solid-State Circuits,2024 (Early Access)
  • Y. -C. Chan, C. -W. Chang and T. -C. Lee, “A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 9, pp. 3263-3267, Sept. 2023
  • Y. -H. Yang, M. Tzou and T. -C. Lee, “A 6.0–11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 2, pp. 386-390, Feb. 2023
  • H. -H. Chang, T. -C. Lin and T. -C. Lee, “A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 4, pp. 2021-2025, April 2022
  • Y. -H. Yang and T. -C. Lee, “A Wireline Termination Embedded Energy Harvesting System With 300-μW Extracted,” in IEEE Solid-State Circuits Letters, vol. 3, pp. 438-441, 2020 (Invited)
  • C. -Y. Lin, Y. -H. Wei and T. -C. Lee, “A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique,” in IEEE Journal of Solid-State Circuits, vol. 53, no. 5, pp. 1508-1517, May 2018
  • C. -T. Tsai et al., “Multi-Mode VCSEL Chip with High-Indium-Density InGaAs/AlGaAs Quantum-Well Pairs for QAM-OFDM in Multi-Mode Fiber,” in IEEE Journal of Quantum Electronics, vol. 53, no. 4, pp. 1-8, Aug. 2017, Art no. 2400608
  • W. -S. Chang and T. -C. Lee, “A 5 GHz Fractional-N ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 11, pp. 1845-1853, Nov. 2016
  • C. -Y. Lin and T. -C. Lee, “A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 7, pp. 929-938, July 2016
  • C. -Y. Lin, C. -H. Wong, C. -H. Hsu, Y. -H. Wei and T. -C. Lee, “A 200-MS/s Phase-Detector-Based Comparator With 400-μVrms Noise,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 9, pp. 813-817, Sept. 2016
  • W-S Chang, P-C Hung and T-C Lee, “A Fractional-N Diver-Less Phase-Locked Loop With a Subsampling Phase Detector” IEEE Journal of Solid-State Circuits, Nov. 2014
  • C-C Lee and T-C Lee, “A 2.4-GHz High Efficiency Adaptive Power Harvester,”IEEE Transactions on Very Large Scale Integration Systems, Feb. 2014
  • C-H Wong and T-C Lee, “A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator,”IEEE Transactions on Circuits and Systems, Part I, vol. 58, no. 3, pp. 1264-1273, May 2013
  • C-D Su, C-W Lee and T-C Lee, “A 6-GHz All Digital PLL for Spread Spectrum Clock Generators(SSCG),” International Journal of Electrical Engineering, Jun. 2012
  • Y-C Huang and T-C Lee, “A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques,” IEEE Transactions on Circuits and Systems, Part I, pp. 1157-1166, Jun. 2011
  • Z-Z Chen and T-C Lee, “The Design and Analysis of Dual-Delay-Path Ring Oscillators,” IEEE Transactions on Circuits and Systems, Part I, Mar. 2011
  • Z-Z Chen and T-C Lee, “The Study of a Dual-Mode Ring Oscillator,” IEEE Transactions on Circuits and Systems, Part II, 2011
  • T-C Lee and C-H Lin, “Nonlinear R-2R Transistor-Only DAC,” IEEE Transactions on Circuits and Systems, Part I, Nov. 2010
  • K-T Chen and T-C Lee, “A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB,” International Journal of Electrical Engineering, Jun. 2010
  • Yen-Chuan Huang and Tai-Cheng Lee, “A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology,” IEEE Journal of Solid-State Circuits, Mar. 2010
  • Li-Han Hung; Tai-Cheng Lee, “A Split-Based Digital Background Calibration Technique in Pipelined ADCs,” IEEE Transactions on Circuits and Systems, Part II, Nov. 2009
  • K-J Hsian and Tai-Cheng Lee, “A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation,” IEEE Journal of Solid-State Circuits, Sept. 2009
  • Zuow-Zun Chen and Tai-Cheng Lee, “A Multiphase Compensation Method with Dynamic Element Matching Technique in S-D Fractional-N Frequency Synthesizers,” Journal of Semiconductor Technology and Science, Sept. 2008
  • K-J Hsiao and T-C Lee, “A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning,” IEEE Journal of Solid-State Circuits, Jun. 2008
  • D.-L. Shen and T.-C. Lee, “A 6-b 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers,” IEEE Journal of Solid-State Circuits, Feb. 2007
  • T.-C. Lee and Y.-C. Huang, “The design and analysis of a Miller Divider Based Clock Generator for MBOA-UWB Application,” IEEE Journal of Solid-State Circuits, Jun. 2006
  • T.-C. Lee and K.-J. Hsiao, “The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application,” IEEE Journal of Solid-State Circuits, Jun. 2006
  • T.-C. Lee and C.-C. Chen, “A Mixed-Signal GFSK Demodulator for Bluetooth,” IEEE Transactions on Circuits and Systems Part II, Mar. 2006
  • T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” IEEE Journal of Solid-State Circuits, Jun. 2003
  • T. C. Lee and B. Razavi, “A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire,” IEEE Journal of Solid-State Circuits, Mar. 2001