Conference Papers

  • C. -T. Chen, Y. -H. Yang and T. -C. Lee, “A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022
  • Y. -P. Lai, H. -H. Chang and T. -C. Lee, “An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter,” 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2022
  • K. -R. Li, W. -S. Chang and T. -C. Lee, “A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique,” 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020
  • H. -C. Cheng, Y. -H. Yang and T. -C. Lee, “Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop,” 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2020
  • Y. -H. Yang and T. -C. Lee, “A Wireline Termination Embedded Energy Harvesting System With 300-μW Extracted,”2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), Hiroshima, Japan, 2020
  • H. -H. Ting and T. -C. Lee, “25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique,” 2020 IEEE International Solid-State Circuits Conference – (ISSCC), San Francisco, CA, USA, 2020
  • Y. -L. Hsieh and T. -C. Lee, “A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling,” 2019 IEEE 13th International Conference on ASIC (ASICON), Chongqing, China, 2019
  • W. -S. Chang, D. -E. Jhou, Y. -H. Yang and T. -C. Lee, “An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique,” 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, Korea (South), 2017
  • J. -C. Hsiao, D. -E. Jhou and T. -C. Lee, “A 10-Gb/s equalizer with digital adaptation,” 2017 International SoC Design Conference (ISOCC), Seoul, Korea (South), 2017
  • D. -E. Jhou, W. -S. Chang and T. -C. Lee, “A 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based MDLL,” 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017
  • H. -Y. Kao et al., “Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link,” 2017 Optical Fiber Communications Conference and Exhibition (OFC), Los Angeles, CA, USA, 2017
  • C. -L. Chang and T. -C. Lee, “An thermoelectric and RF multi-source energy harvesting system,” 2016 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG), Prague, Czech Republic, 2016
  • Y. -H. Wei, C. -Y. Lin and T. -C. Lee, “A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration,” 2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Taipei, Taiwan, 2016
  • C. -P. Wang and T. -C. Lee, “A technique for in-band phase noise reduction in fractional-N frequency synthesizers,” 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, Japan, 2016
  • B-J Lin, W-S Chang and T-C Lee, “A 2x25Gb/s 20mW Serializing Transmitter with 2.5:1 Multiplexers in 40nm Technology”IEEE International Symposium on VLSI Design, Automation and Test, April 2016
  • C-Y Lin, Y-H Wei and T-C Lee, “A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration” International Solid-State Circuit Conference, San Francisco, Feb. 2016
  • C-K Hsu and T-C Lee, “ A Single-Channel 10-b 400-MS/s 8.7-mW Pipeline ADC in a 90-nm Technology” IEEE Asian Solid-State Circuit Conference, Nov. 2015
  • T-Y Wang and T-C Lee, “A 84.7-DR wide BW incremental ADC using  CT structure” IEEE International Symposium on VLSI Design, Automation and Test, April 2015
  • C-L Chang and T-C Lee, “A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability” IEEE International Symposium on Integrated Circuits, Dec. 2014
  • L-H Chiueh and T-C Lee, “A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit” IEEE Asian Solid-State Circuit Conference, Nov. 2014
  • C-Y Lin and T-C Lee, “A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique” IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2014
  • J-A Jheng, W-S Chang and T-C Lee, “A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth” IEEE International Symposium on VLSI Design, Automation and Test, April 2014.
  • P-C Huang, W-S Chang and T-C Lee, “A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise,” International Solid-State Circuit Conference, San Francisco, Feb. 2014
  • C-Y Lin and T-C Lee, “Jitter Error Cancellation Technique in Digital Domain for ADC,” IEEE VLSI-DAT, Apr. 2013
  • C-Y Lin Y-C Huang and T-C Lee, “Analysis of the Leakage Effect in a Pipelined ADC with Nanoscale CMOS Technologies,” IEEE VLSI-DAT, Apr. 2013
  • C-C Ho and T-C Lee, “A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter,” IEEE VLSI DAT, Apr. 2012
  • Y-C Huang, C-Y Lin and T-C Lee, “A 10-b 400Ms/s 36mW interleaved ADC,” IEEE RFIT Symposium, Dec. 2011
  • P Zhang, T-C Lee, “Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS,” International Conference on Sampling Theory and Applications, May 2011
  • K Fong, Z-Z Chen and T-C Le, “An All‐Digital De‐skew Clock Generator for Arbitrary Wide Range Delay,” IEEE Asian Pacific Conference on Circuits and Systems, Dec. 2010
  • Y-C Hung, K Fong and T-C Lee, “A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay,” IEEE Asian Solid-State Circuit Conference, Nov. 2010
  • C-Y Lin, C-Y Chiang and T-C Lee, “An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III,” IEEE Custom Integrated Circuits Conference, Sept. 2010
  • Yen-Chuang Huang and Tai-Cheng Lee, “A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques,” International Solid-State Circuit Conference, San Francisco, Feb. 2010
  • Feng-Chiu Hsieh and Tai-Cheng, “A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification,” IEEE Asian Solid-State Circuit Conference, Fukuoka, Japan, Nov. 2008
  • Shih-Chun Lin and Tai-Cheng Lee, “An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits,” IEEE Aisan Solid-State Circuit Conference, Fukuoka, Japan, Nov. 2008
  • K-J Hsiao, M-H Lee and T-C Lee, “A CLOCK AND DATA RECOVERY CIRCUIT WITHWIDE LINEAR RANGE FREQUENCY,” IEEE VLSI-DAT, Apr. 2008
  • Y-C Huang, Q-T Chen and T-C Lee, “A 4-PAM Adaptive Analog Equalizer for Backplane Interconnections,” IEEE VLSI-DAT, Apr. 2008
  • K-J Hsiao and T.-C. Lee, “A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation,” IEEE International Solid-State Circuit Conference, Feb. 2008
  • D.-L Shen, Y-C Lai and T.-C. Lee, “A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration,” IEEE Asian Solid-State Circuit Conference, Nov. 2007
  • K-J Hsiao and T-C Lee, “A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning,” Symposium on VLSI Circuits, Jun. 2007
  • G-J Chen, H-H Chiu and T-C Lee, “A 4-Channel Poly-Phase Filter for Cognitive Radio Systems,” IEEE VLSI-DAT, Apr. 2007
  • H-S Kao, M-J Yang, T-C Lee, “A Delay-Line-Based GFSK Demodulator for Low-IF Receivers,” International Solid-State Circuit Conference (ISSCC), Feb. 2007
  • Q.-T. Chen, Y.-C. Huang and T.-C. Lee, “A 14Gb/s 4PAM Adaptive Analog Equalizer for 40-inch Backplane Interconnections,” Asian Solid-State Circuit Conference (ASSCC), Nov. 2006
  • D-L Shen and T-C Lee, “A 6-b 800-MS/s Pipelined A/D Converter with Open-loop Amplifiers,” IEEE Symposium on VLSI Circuits, Jun. 2006
  • Y-M Liao and T-C Lee, “A 6-b 1.3Gs/s A/D Converter with C-2C Switch–Capacitor Technique,” IEEE VLSI-DAT, Apr. 2006
  • T.-C. Lee and W.-L. Lee, “A Spur-Suppression Technique for Phase-Locked Frequency Synthesizers,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2006
  • T.-C. Lee and etal, “A 40-GHz Distributed-Load Static Divider,” IEEE Asian Solid-State Circuit Conference, Nov. 2005
  • T. C. Lee and K-J Hsiao, “A DLL-Based Frequency Multiplier For MBOA-UWB System,” IEEE Symposium on VLSI Circuits, Jun. 2005
  • T. C. Lee and Y. C. Huang, “A Miller Divider Based Clock Generator for MBOA-UWB Application,” IEEE Symposium on VLSI Circuits, Jun. 2005
  • D. L. Shen and T. C. Lee, “A Linear-Approximation Technique for Digitally-Calibrated Pipelined ADCs,” ISCAS, May 2005
  • T. C. Lee and Y. C. Huang, “An Optimization Technique for RF Buffers with Active Inductors,” ISCAS, May 2005
  • Y. H. Chen, and T. C. Lee, “6 bits 500-Ms/s Digital Self-Calibrated Pipelined Analog-to-Digital Converter,” AP-ASIC, pp98-101, Aug. 2004
  • H. C. Wang, H. S. Kao, and T. C. Lee, “An 8-bit 2-V 2-mW 0.25-mm2 CMOS DAC,” AP-ASIC, pp. 102-105, Aug. 2004
  • T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers,” IEEE VLSI Circuits Symposium, Kyoto, Japan, Jun. 2001
  • T. C. Lee and B. Razavi, “A 125-MHz Mixed-Signal Equalizer for Gigabit Ethernet on Copper Wire,” IEEE Custom Integrated Circuits Conference, San Diego, May 2001
  • T. C. Lee and B. Razavi, “A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire,” IEEE Custom Integrated Circuits Conference, Orlando, May 2000